Complementary metal oxide semiconductor (CMOS) integrated circuit structures employ complementary insulated gate field effect transistor (IGFET) devices to perform the active circuit functions. The structures involved can also include active bipolar junction transistor (BJT) devices. In a typical prior art CMOS input buffer the usual approach is to employ a conventional inverter having the N channel and P channel devices ratioed to provide the desired switching threshold. The TTL logic levels of 0.8 volt or below for a logic low and 2 volts or above for a logic high are such that for a logic high input both inverter transistors will normally conduct and therefore dissipate power. Regenerative circuit elements can be added to the inverter to aid in logic level discrimination, but these too dissipate power. When the circuit application calls for a large number of input buffers the power dissipation can become a significant problem.